From 01e80eefc05d8bca9d301b083eec1763d788a9ee Mon Sep 17 00:00:00 2001 From: Christian Dresel Date: Sat, 24 Nov 2018 00:28:58 +0100 Subject: [PATCH 2/3] Enable-QinQ-on-the-switch Signed-off-by: Christian Dresel --- .../715-ar40xx-Enable-QinQ-on-the-switch.patch | 86 ++++++++++++++++++++++ 1 file changed, 86 insertions(+) create mode 100644 target/linux/ipq40xx/patches-4.14/715-ar40xx-Enable-QinQ-on-the-switch.patch diff --git a/target/linux/ipq40xx/patches-4.14/715-ar40xx-Enable-QinQ-on-the-switch.patch b/target/linux/ipq40xx/patches-4.14/715-ar40xx-Enable-QinQ-on-the-switch.patch new file mode 100644 index 0000000..c8edcbf --- /dev/null +++ b/target/linux/ipq40xx/patches-4.14/715-ar40xx-Enable-QinQ-on-the-switch.patch @@ -0,0 +1,86 @@ +From: Sven Eckelmann +Date: Fri, 17 Mar 2017 11:04:50 +0100 +Subject: [PATCH] ar40xx: Enable QinQ on the switch + +The switch used in by IPQ40xx is using VLANs by default to select the +outgoing port. It was therefore not possible to sent or receive 802.1q +tagged frames over the CPU port. This can be allowed by changing the port +configuration and lookup configuration. + +The resulting VLAN-tagged frames send or received by the CPU will therefore +look like QinQ frames. The outer VLAN tag is the port-VLAN of the port from +which the data was received or towards which the data has to be sent. The +inner VLAN tag (when it exists) is the VLAN which was configrued on top of +the ethernet device. + +--- + +diff --git a/drivers/net/phy/ar40xx.c b/drivers/net/phy/ar40xx.c +--- a/drivers/net/phy/ar40xx.c ++++ b/drivers/net/phy/ar40xx.c +@@ -1246,6 +1246,10 @@ ar40xx_init_globals(struct ar40xx_priv *priv) + t = (AR40XX_PORT0_FC_THRESH_ON_DFLT << 16) | + AR40XX_PORT0_FC_THRESH_OFF_DFLT; + ar40xx_write(priv, AR40XX_REG_PORT_FLOWCTRL_THRESH(0), t); ++ ++ /* set service tag to 802.1q */ ++ //t = ETH_P_8021Q | AR40XX_ESS_SERVICE_TAG_STAG; ++ //ar40xx_write(priv, AR40XX_ESS_SERVICE_TAG, t); + } + + static void +@@ -1571,7 +1575,11 @@ ar40xx_setup_port(struct ar40xx_priv *priv, int port, u32 members) + u32 pvid = priv->vlan_id[priv->pvid[port]]; + + if (priv->vlan) { +- egress = AR40XX_PORT_VLAN1_OUT_MODE_UNMOD; ++ //if (priv->vlan_tagged & BIT(port)) ++ // egress = AR40XX_PORT_VLAN1_OUT_MODE_TAG; ++ //else ++ egress = AR40XX_PORT_VLAN1_OUT_MODE_UNMOD; ++ + ingress = AR40XX_IN_SECURE; + } else { + egress = AR40XX_PORT_VLAN1_OUT_MODE_UNTOUCH; +@@ -1582,8 +1590,17 @@ ar40xx_setup_port(struct ar40xx_priv *priv, int port, u32 members) + t |= pvid << AR40XX_PORT_VLAN0_DEF_CVID_S; + ar40xx_write(priv, AR40XX_REG_PORT_VLAN0(port), t); + +- t = AR40XX_PORT_VLAN1_PORT_VLAN_PROP; +- t |= egress << AR40XX_PORT_VLAN1_OUT_MODE_S; ++ t = egress << AR40XX_PORT_VLAN1_OUT_MODE_S; ++ ++ ///* set CPU port to core port */ ++ //if (port == 0) ++ // t |= AR40XX_PORT_VLAN1_CORE_PORT; ++ ++ //if (priv->vlan_tagged & BIT(port)) ++ t |= AR40XX_PORT_VLAN1_PORT_VLAN_PROP; ++ //else ++ // t |= AR40XX_PORT_VLAN1_PORT_TLS_MODE; ++ + ar40xx_write(priv, AR40XX_REG_PORT_VLAN1(port), t); + + t = members; +diff --git a/drivers/net/phy/ar40xx.h b/drivers/net/phy/ar40xx.h +--- a/drivers/net/phy/ar40xx.h ++++ b/drivers/net/phy/ar40xx.h +@@ -151,6 +151,9 @@ struct ar40xx_mib_desc { + #define AR40XX_MIB_FUNC_NO_OP 0x0 + #define AR40XX_MIB_FUNC_FLUSH 0x1 + ++#define AR40XX_ESS_SERVICE_TAG 0x48 ++#define AR40XX_ESS_SERVICE_TAG_STAG BIT(17) ++ + #define AR40XX_REG_PORT_STATUS(_i) (0x07c + (_i) * 4) + #define AR40XX_PORT_SPEED BITS(0, 2) + #define AR40XX_PORT_STATUS_SPEED_S 0 +@@ -179,6 +182,8 @@ struct ar40xx_mib_desc { + #define AR40XX_PORT_VLAN0_DEF_CVID_S 16 + + #define AR40XX_REG_PORT_VLAN1(_i) (0x424 + (_i) * 0x8) ++#define AR40XX_PORT_VLAN1_CORE_PORT BIT(9) ++#define AR40XX_PORT_VLAN1_PORT_TLS_MODE BIT(7) + #define AR40XX_PORT_VLAN1_PORT_VLAN_PROP BIT(6) + #define AR40XX_PORT_VLAN1_OUT_MODE BITS(12, 2) + #define AR40XX_PORT_VLAN1_OUT_MODE_S 12 -- 2.7.4